The subject matter disclosed herein relates to solutions for photomask design verification. More specifically, the subject matter disclosed herein relates to using a plurality of process models and verification techniques to improve the accuracy of printed photomasks.
As semiconductor devices decrease in size, fabrication processes are refined to create smaller device designs. As a result, resolution limits of the tools and materials used to fabricate these smaller semiconductor devices are tested. In order to prevent failures in design configurations, fabricators have specified design rules for device designers to follow. While these design rules aid in reducing failures during fabrication, they can be overly restrictive on designers and may not be modified frequently enough to keep designs competitive.